Low Power Soft-Error Hardened Latch Implemented by Carbon Nanotube Field-Effect Transistors

Document Type : Research Paper


1 Department of Electrical Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran

2 Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran


   A soft error hardened latch is designed, which is based on carbon nanotube field-effect transistors (CNTFETs). The nanoscale circuits are more susceptible to transient or soft errors due to reduced stored charge in their sensitive nodes. Hence, an energy efficient design is a significant challenge, particularly for storage elements like latches. The proposed hardened latch consists of a Schmitt trigger circuit to mask the transient errors, a memory cell, and a C-element with an inverter at its output. The delay element followed by a C-element and a memory cell structure filters single event transient (SET) effectively and has improved robustness against single event upset (SEU). CNTFETs are substituted to gain all the benefits of nanotubes, such as robustness, temperature stability, high speed, and low power consumption. The implementation results in 32nm technology indicate a power consumption of 11.33nW for the supply voltage of 0.9V. The designed latch has low power consumption and lower power-delay product (PDP) concerning the design in CMOS technology. Compared to reported CNTFET latches, the simulation results indicate that, in addition to lower area requirement the proposed latch is more resistant to energetic particles strike than other similar latches and the rise and fall time of the proposed structure is between 12 to 15 ps in different conditions.


Main Subjects

  1. Knight, J. C., "Safety critical systems: challenges and directions", Proceedings of the 24th international conference on software engineering, (2002).
  2. Constantinescu, C., "Impact of deep submicron technology on dependability of VLSI circuits", Proceedings International Conference on Dependable Systems and Networks, (2002).
  3. Reviriego, P., Maestro, J. A., Cervantes, C., "Reliability analysis of memories suffering multiple bit upsets", IEEE Transactions on Device and Materials Reliability, 7(4) (2007) 592-601.
  4. Alioto, M., "Ultra-low power VLSI circuit design demystified and explained: A tutorial", IEEE Transactions on Circuits and Systems I, 59(1) (2012) 3-29.
  5. Kim, Y.-B., "Challenges for nanoscale MOSFETs and emerging nanoelectronics", Transactions on Electrical and Electronic Materials, 11(3) (2010) 93-105.
  6. Qi, C., "A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets", IEEE Transactions on Device and Materials Reliability, 16(3) (2016) 388-395.
  7. NS, A. K. P., Baghini, M. S., "Robust soft error tolerant CMOS latch configurations", IEEE transactions on computers, 65(9) (2015) 2820-2834.
  8. Seifert, N., Zhu, X., Massengill, L. W., "Impact of scaling on soft-error rates in commercial microprocessors", IEEE Transactions on Nuclear Science, 49(6) (2002) 3100-3106.
  9. Baumann, R. C., "Radiation-induced soft errors in advanced semiconductor technologies", IEEE Transactions on Device and materials reliability, 5(3) (2005) 305-316.
  10. Lee, H.-H. K., "Design framework for soft-error-resilient sequential cells", IEEE Transactions on Nuclear Science, 58(6) (2011) 3026-3032.
  11. Islam, R., "A highly reliable SEU hardened latch and high performance SEU hardened flip-flop", Thirteenth International Symposium on Quality Electronic Design (ISQED), (2012).
  12. Seifert, N., "Radiation-induced clock jitter and race", IEEE International Reliability Physics Symposium, Proceedings, 43rd Annual, (2005).
  13. Chandra, V., Aitken, R.,."Impact of technology and voltage scaling on the soft error susceptibility in nanoscale CMOS", IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, (2008).
  14. Qi, C., "Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology", Microelectronics Reliability, 55(6) (2015) 863-872.
  15. Kim, L. -S., Dutton, R. W., "Metastability of CMOS latch/flip-flop", IEEE Journal of solid-state circuits, 25(4) (1990) 942-951.
  16. Omana, M., Rossi, D., Metra, D., "Novel Transient Fault Hardened Static Latch", ITC., (2003).
  17. Shirinzadeh, S., Asli, R. N., "A novel soft error hardened latch design in 90nm CMOS", 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), (2012).
  18. Karnik, T., "Selective node engineering for chip-level soft error rate improvement [in cmos]", Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No. 02CH37302), (2002).
  19. Harris, D., Weste, N., "Cmos vlsi design", ed: Pearson Education, Inc, (2010).
  20. Peng, C., "Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(2) (2018) 407-415.
  21. Li, Y.-Q., "A quatro-based 65-nm flip-flop circuit for soft-error resilience", IEEE Transactions on Nuclear Science, 64(6) (2017) 1554-1561.
  22. Yan, A., "Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications", IEEE 28th Asian Test Symposium (ATS), (2019).
  23. Mitra, S., "Logic soft errors: a major barrier to robust platform design", IEEE International Conference on Test, (2005).
  24. Shivakumar, P., "Modeling the effect of technology trends on the soft error rate of combinational logic", Proceedings International Conference on Dependable Systems and Networks, (2002).
  25. Baumann, R., "Soft errors in advanced computer systems", IEEE Design & Test of Computers, 22(3) (2005) 258-266.
  26. Calin, T., Nicolaidis, M., Velazco, R., "Upset hardened memory design for submicron CMOS technology", IEEE Transactions on nuclear science, 43(6) (1996) 2874-2878.
  27. Hazucha, P., "Measurements and analysis of SER-tolerant latch in a 90-nm dual-Vт CMOS process", IEEE Journal of Solid-State Circuits, 39(9) (2004) 1536-1543.
  28. Stackhouse, B., "A 65 nm 2-billion transistor quad-core Itanium processor", IEEE Journal of Solid-State Circuits,.44(1) (2008) 18-31.
  29. She, X., McElvain, K., "Time multiplexed triple modular redundancy for single event upset mitigation", IEEE Transactions on nuclear science, 56(4) (2009) 2443-2448.
  30. Fazeli, M., "Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies", IET computers & digital techniques, 3(3) (2009) 289-303.
  31. Omana, M., Rossi, D., Metra, C., "Latch susceptibility to transient faults and new hardening approach", IEEE Transactions on Computers,.56(9) (2007) 1255-1268.
  32. Iijima S. Helical, "Microtubulesof graphitic carbon", Nature, 354 (1991) 56.
  33. Lin, S., Kim, Y.-B., Lombardi, F., "CNTFET-based design of ternary logic gates and arithmetic circuits", IEEE transactions on nanotechnology, 10(2) (2009) 217-225.
  34. Deng, J., "Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field effect transistors", Stanford University, (2007).
  35. Akinwande, D. A., "Carbon Nanotubes: Device Physics, RF Circuits, Surface Science, and Nanotechnology", Stanford University, (2010).
  36. Moaiyeri, M. H., "Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits", Journal of applied research and technology, 15(3) (2017) 233-241.
  37. Omaña, M., Rossi, D., Metra, C., "High-performance robust latches", IEEE Transactions on Computers, 59(11) (2010) 1455-1465.
  38. Glorieux, M., "New D-flip-flop design in 65 nm CMOS for improved SEU and low power overhead at system level", IEEE Transactions on Nuclear Science,.60(6) (2013) 4381-4386.
  39. Rajaei, R., Tabandeh, M., Fazeli, M., "Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation", Microelectronics Reliability, 53(6) (2013) 912-924.
  40. Marani, R., Perri A. G., “A Comparison of CNTFET and CMOS technology through the Design of a SRAM Cell”, ECS Journal of Solid-State Science and Technology, 8(1) (2019) 1-18.
  41. Marani, R., Perri, A. G., “Impact of Technology on CNTFET-based Circuits Performance”, ECS Journal of Solid-State Science and Technology, 9(5) (2020).
  42. Marani, R., Perri, A. G., “A Procedure to Analyze a CNTFET-based NOT gate with Parasitic Elements of Interconnection Lines”, International Journal of Nanoscience and Nanotechnology, 17(3) (2021) 161-171.
  43. Abhay S. Vidhyadharan, Vidhyadharan, S., “A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM”, Microelectron. J., 111 (2021) 105033.