Reducing Hardware Complexity of Wallace Multiplier Using High Order Compressors Based on CNTFET

Document Type : Research Paper


1 Technical Engineering Department, University of Mohaghegh Ardabili, Ardabil, Iran

2 Faculty of Technical Engineering Department, University of Mohaghegh Ardabili, Ardabil, Iran

3 Nano technology and Quantum Computing Lab, Shahid Beheshti University, GC, Tehran, Iran


   Multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. Improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. Wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and reduce the area of multipliers. Compressors are adders which can be used to perform the partial product addition in Wallace tree. On the other hand, using new emerging technologies such as Carbon Nanotube Field Effect Transistors (CNTFET) leads to provide implementations faster and smaller circuits. This paper presents a new method to reduce the simplification of Wallace tree design using high order compressors based on carbon nanotube technology. These compressors use a high-speed full adder cell based on CNTFETs for low-voltage and high-frequency applications. The proposed method reduces the number of gates and transistors, critical path length and complexity of the Wallace tree hardware.


1.      Khatibzadeh, A., Raahemifar, K. (2005). "A novel pipelined multiplier for high-speed DSP applications", International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005., IEEE.          
2.      Al-Khaleel, O., Chris, P., Frank, W., Kiamal, P. (2006). "A large scale adaptable multiplier for cryptographic applications", First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06), IEEE.       
3.      Rouholamini, M., Mahnoush., Omid, K., Amir-Pasha, M., Somaye, J.,Keivan., N. (2007). "A new design for 7: 2 compressors", 2007 IEEE/ACS International Conference on Computer Systems and Applications, IEEE.        
4.      Oklobdzija, V. G., David, V.,Simon, S. Liu (1996). "A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach", IEEE Transactions on Computers 45(3): 294-306.       
5.      Sureka, N., Porselvi, R., Kumuthapriya, K., Kumuthapriya, K.. (2013). "An efficient high speed Wallace tree Multiplier", Information Communication and Embedded Systems (ICICES), 2013 International Conference on, IEEE.  
6.      Samdaliri, S., Javidan, J., Sam, M., Navi, K. (2015). "Design of a new high-speed and high-performance Full Adder   Cell Based on Carbon Nanotube FETs", Quntum Matter, 5: 524-528.     
7.      Moaiyeri, M. H., Faghih Mirzaee, R., Navi, K., Momeni, A. (2012). "Design and analysis of a high-performance CNFET-based Full Adder", International Journal of Electronics, 99(1): 113-130.            
8.      Reshadinezhad, M. R., Moaiyeri, M. H., Navi, K. (2012). "An energy-efficient full adder cell using CNFET technology", IEICE transactions on electronics 95(4): 744-751.  
9.      Navi, K., Sharifi Rad, R., Moaiyeri, M. H., Momeni, A. (2010). "A low-voltage and energy-efficient full adder cell based on carbon nanotube technology", Nano-Micro Letters, 2(2): 114-120.            
10.    Moaiyeri, M. H., Navi, K., Hashemipour, O. (2012). "Design and evaluation of CNFET-based quaternary circuits", Circuits, Systems, and Signal Processing, 31(5): 1631-1652.           
11.    Sajedi, H. H., Sam, M., Navi, K., Jalali, A. (2015). "High Performance and Low Power Half-Adder Cells in Carbon Nanotube Field Effect Transistor Technology", Journal of Computational and Theoretical Nanoscience, 12(8): 1756-1760. 
12.    Sam, M., Navi, K., Moaiyeri, M.H. (2016). "A New 5-Input Molecular Exclusive-OR Gate Based on Benzene Ring and Carbon Nanotube FETs", Quantum Matter, 5(1): 99-102. 
13.    Lin, S., Yong-Bin, K., Lombardi, F. (2011). "CNTFET-based design of ternary logic gates and arithmetic circuits", IEEE transactions on nanotechnology, 10(2): 217-225.      
14.    Farhadian, N. (2013). "Investigating the Ibuprofen Chiral Forms Interactions with Single Wall Carbon Nanotube", International Journal of Nanoscience and Nanotechnology, 9(3): 127-138.     
15.    Farhadian, N., Shariaty-Niassar, M. (2009). "Molecular Dynamics Simulation of Water in Single WallCarbon Nanotube", International Journal of Nanoscience and Nanotechnology, 5(1): 53-62.              
16.    Deng, J., Wong, H.-S. P. (2007). "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region", IEEE Transactions on Electron Devices, 54(12): 3186-3194.   
17.    Deng, J., Wong, H.-S. P. (2007). "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking", IEEE Transactions on Electron Devices, 54(12): 3195-3205.     
18.    Chang, C.-H., Gu, J., Zhang, M. (2004). "Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits", IEEE Transactions on Circuits and Systems, I: Regular Papers, 51(10): 1985-1997.
19.    Radhakrishnan, D., Preethy, A. (2000). "Low power CMOS pass logic 4-2 compressor for high-speed multiplication", PROCEEDINGS OF THE IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, LIDA RAY TECHNOLOGIES INC.        
20.    Rebala, N. R., krishna Tirumala, B. (2014). "High speed multipliers using nested higher order compressors", 2014 International Conference on Computer Communication and Informatics.     
21.    Koren, I. (2002). "Computer arithmetic algorithms", Universities Press.              
22.    Akoushideh, A., Ardalan, Najafi., Babak, Mazloom-nezhad Maybodi. (2012). "Modified Architecture for 27: 2 Compressor", Canadian Journal on Electrical and Electronics Engineering.            
23.    Khan, S., Sandeep, Kakde., Yogesh, Suryawanshi. (2013). "VLSI implementation of reduced complexity wallace multiplier using energy efficient CMOS full adder", Computational Intelligence and Computing Research (ICCIC), 2013 IEEE International Conference on, IEEE.     
24.    Aguirre-Hernandez, M., Linares-Aranda, M. (2011). "CMOS full-adders for energy-efficient arithmetic applications", IEEE transactions on very large scale integration (VLSI) systems, 19(4): 718-721.       
25.    Mirzaee, R. F., Keivan, N. (2014). "Optimized adder cells for ternary ripple-carry addition", IEICE TRANSACTIONS on Information and Systems, 97(9): 2312-2319.