Iranian Nanotechnology Society International Journal of Nanoscience and Nanotechnology 1735-7004 20 2 2024 05 31 A Procedure to Compare CNTFET and CMOS Technologies through the Design of a SRAM Cell: A Review 113 127 715068 10.22034/ijnn.2024.2021428.2472 EN Roberto Marani Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy Anna Gina Perri Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy 0000-0003-4949-987X Journal Article 2024 01 28    <em>In this paper we review in depth a procedure to compare the performance of CNTFET and MOSFET devices operating in sub-threshold region for ultra-low power applications. This aim is obtained through the design of a SRAM cell. The first design is based on our CNTFET model, while for the second one we use the BSIM4 model of the ADS library. At last the comparison between the two considered technologies are quantitatively presented, showing and discussing the improvements obtained with CNTFET technology</em><em>. </em><em>All simulations are carried out</em><em> using the software Advanced Design System (ADS), which is compatible with the Verilog-A programming language, </em><em>avoiding so the problems presented in SPICE</em><em> used in previous designs proposed in literature.</em> https://www.ijnnonline.net/article_715068_599cf98fa499929b7dde0597877d1168.pdf