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<Journal>
				<PublisherName>Iranian Nanotechnology Society</PublisherName>
				<JournalTitle>International Journal of Nanoscience and Nanotechnology</JournalTitle>
				<Issn>1735-7004</Issn>
				<Volume>20</Volume>
				<Issue>1</Issue>
				<PubDate PubStatus="epublish">
					<Year>2024</Year>
					<Month>03</Month>
					<Day>01</Day>
				</PubDate>
			</Journal>
<ArticleTitle>Impact of the CNT Parameter Variations on Performance of Digital Circuits Based on CNTFET</ArticleTitle>
<VernacularTitle></VernacularTitle>
			<FirstPage>33</FirstPage>
			<LastPage>46</LastPage>
			<ELocationID EIdType="pii">711962</ELocationID>
			
<ELocationID EIdType="doi">10.22034/ijnn.2024.2014292.2447</ELocationID>
			
			<Language>EN</Language>
<AuthorList>
<Author>
					<FirstName>Roberto</FirstName>
					<LastName>Marani</LastName>
<Affiliation>Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing (STIIMA), National Research Council of Italy, 70125, Bari, Italy</Affiliation>

</Author>
<Author>
					<FirstName>Anna Gina</FirstName>
					<LastName>Perri</LastName>
<Affiliation>Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy</Affiliation>
<Identifier Source="ORCID">0000-0003-4949-987X</Identifier>

</Author>
</AuthorList>
				<PublicationType>Journal Article</PublicationType>
			<History>
				<PubDate PubStatus="received">
					<Year>2023</Year>
					<Month>02</Month>
					<Day>05</Day>
				</PubDate>
			</History>
		<Abstract>&lt;em&gt;   In this paper we propose a method to study the impact of the CNT parameter variations on performance of CNTFET digital circuits. In particular we consider CNT parameters that fully identify the geometrical properties of a regular CNT, which are the length and structural indices (n, m) of CNT. We analyse in particular the effects on NAND gate using a N and P type CNTFET, polarizing at a fixed voltage and varying the CNT parameters.  As regards the indices, we limit the analysis to zig-zag CNT, highlighting that &lt;/em&gt;&lt;em&gt;the proposed procedure can be applied to other types of CNT&lt;/em&gt;&lt;em&gt;.&lt;/em&gt;</Abstract>
		<ObjectList>
			<Object Type="keyword">
			<Param Name="value">nanoelectronics</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Nanodevices</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">CNT</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">CNTFET</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Modelling</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Digital circuits</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Verilog-A</Param>
			</Object>
		</ObjectList>
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