Iranian Nanotechnology Society International Journal of Nanoscience and Nanotechnology 1735-7004 17 3 2021 08 01 A Procedure to Analyze a CNTFET-Based ‎NOT Gate with Parasitic Elements of ‎Interconnection Lines 161 171 245846 EN R. Marani ‎Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing ‎‎(STIIMA), National Research Council of Italy, 70125, Bari, Italy‎ 0000-0002-5599-903X A. G. Perri ‎Electronic Devices Laboratory, Department of Electrical and Information Engineering, ‎Polytechnic University of Bari, 70126, Bari, Italy 0000-0003-4949-987X Journal Article 2021 06 25    <em>In this paper we analyze an application of CNTFET in the design of NOT gate, in which parasitic elements of interconnection lines are considered. At first we study the time domain analysis of NOT gate without to consider the parasitic elements of interconnection lines, in order to compare the obtained results with those in which the parasitic elements are considered, showing how they limit the high-speed performances of CNTs.</em> https://www.ijnnonline.net/article_245846_f9d00121ba90dc2eab067a6ee61af6db.pdf