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<Article>
<Journal>
				<PublisherName>Iranian Nanotechnology Society</PublisherName>
				<JournalTitle>International Journal of Nanoscience and Nanotechnology</JournalTitle>
				<Issn>1735-7004</Issn>
				<Volume>17</Volume>
				<Issue>1</Issue>
				<PubDate PubStatus="epublish">
					<Year>2021</Year>
					<Month>03</Month>
					<Day>01</Day>
				</PubDate>
			</Journal>
<ArticleTitle>Design of Encoder Circuit Using Layered ‎NAND and NOR Gates in Quantum Dot ‎Cellular Automata ‎</ArticleTitle>
<VernacularTitle></VernacularTitle>
			<FirstPage>11</FirstPage>
			<LastPage>21</LastPage>
			<ELocationID EIdType="pii">242799</ELocationID>
			
			
			<Language>EN</Language>
<AuthorList>
<Author>
					<FirstName>R.</FirstName>
					<LastName>Chakrabarty</LastName>
<Affiliation>‎Department of Electronics &amp; Communication Engineering, Institute of Engineering &amp; ‎Management, Salt Lake, Kolkata, West Bengal 700091, India‎</Affiliation>

</Author>
<Author>
					<FirstName>N. K.</FirstName>
					<LastName>Mandal</LastName>
<Affiliation>‎Department of Electronics &amp; Communication Engineering, University of Engineering &amp; ‎Management, Newtown, Kolkata, West Bengal 700160, India‎</Affiliation>

</Author>
</AuthorList>
				<PublicationType>Journal Article</PublicationType>
			<History>
				<PubDate PubStatus="received">
					<Year>2020</Year>
					<Month>01</Month>
					<Day>30</Day>
				</PubDate>
			</History>
		<Abstract>&lt;em&gt;   Quantum dot cellular automata or QCA represents a new methodology of quantum computing with the potential for higher performance over existing devices.&lt;/em&gt;&lt;em&gt;It adds necessary features such as enhanced speed, smaller size and lower power consumption in comparison to existing CMOS based technology. Based on this study the proposed paper designed three &lt;/em&gt;&lt;em&gt;different kinds of encoder circuits using QCA technology. Following paper used layered 2-input NAND gate and NOR gates to design 4 to 2 encoder, priority encoder and octal to binary encoder circuits. The paper also showed the cell count, area, length, breadth &amp; latency calculations for the designed encoder circuits. Proposed circuits are compared with the previously suggested designs in terms of area consumption and cell count. All the circuits designed without majority gate circuit. Potential energy for the designed circuits also calculated to check the stable output and reliability of the circuits. &lt;/em&gt;</Abstract>
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			<Object Type="keyword">
			<Param Name="value">Quantum-dot cellular Automata</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Layered NAND Gate</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Layered NOR Gate</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Priority Encoder</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Latency</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">‎Polarization</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Octal to binary encoder. ‎</Param>
			</Object>
		</ObjectList>
<ArchiveCopySource DocType="pdf">https://www.ijnnonline.net/article_242799_347867b574298f12029f4c24c563bbe4.pdf</ArchiveCopySource>
</Article>
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