%0 Journal Article
%T Analysis of Temperature Effects in the Design of NOT Gate Based on CNTFET
%J International Journal of Nanoscience and Nanotechnology
%I Iranian Nanotechnology Society
%Z 1735-7004
%A Marani, R.
%A Perri, A. G.
%D 2022
%\ 08/01/2022
%V 18
%N 3
%P 167-177
%! Analysis of Temperature Effects in the Design of NOT Gate Based on CNTFET
%K CNTFET
%K Modelling
%K temperature effects
%K NOT gate
%K Verilog-A
%K Computer Aided Design (CAD)
%R
%X This paper presents a procedure to analyze the effects of temperature in CNTFET-based NOT gate using a compact semi-empirical model, already proposed by us. The proposed analysis allows to determine the noise margin and static power in different voltage supplies and temperature conditions. In particular the noise margin decreases and static power increases with temperature, so it can be asserted that low temperature is the most advantageous condition. This is true except for the case 100 K - 200 mV where noise margin is much lower than the expected value due to the double peak in gain function. In terms of power, it should be also noted that decreasing temperature from 200 K to 100 K does not produce any remarkable result. The proposed procedure can be applied to analyze the effects of temperature in the design of A/D circuits based on CNTFET.
%U https://www.ijnnonline.net/article_254341_af822dbd70293ea7135a686552d9e88a.pdf