International Journal of Nanoscience and Nanotechnology

International Journal of Nanoscience and Nanotechnology

A Technique, Based on Thevenin Equivalent Method, to Study the Noise Performance of Analog Circuits Involving both CNTFET and MOS Devices

Document Type : Research Paper

Authors
Roberto Marani 1
Anna Gina Perri 2
1 Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing (STIIMA), National Research Council of Italy, 70125, Bari, Italy
2 Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy
10.22034/ijnn.2023.1988468.2327
Abstract
   This paper presents a procedure, based on Thevenin equivalent method, to analyse the noise effects in analog circuits based on CNTFET and MOS devices. To achieve this goal, we use a semi-empirical compact CNTFET model, already proposed by us, including noise source contributions, and the BSIM4 model for MOS device. After a brief review of these models, as example of analog circuit, the proposed procedure is applied to study a basic current mirror and the simulation results allow to determine easily the different noise contribution of every single source. The software used is Advanced Design System (ADS) which is compatible with the Verilog-A programming language.
Keywords
CNTFET
MOSFET
Modelling
Noise Effects
Analog circuits
Advanced Design System

Subjects

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International Journal of Nanoscience and Nanotechnology
Volume 19, Issue 1
Winter 2023
Pages 9-19