A Technique, Based on Thevenin Equivalent Method, to Study the Noise Performance of Analog Circuits Involving both CNTFET and MOS Devices

Document Type : Research Paper

Authors

1 Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing (STIIMA), National Research Council of Italy, 70125, Bari, Italy

2 Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy

Abstract

   This paper presents a procedure, based on Thevenin equivalent method, to analyse the noise effects in analog circuits based on CNTFET and MOS devices. To achieve this goal, we use a semi-empirical compact CNTFET model, already proposed by us, including noise source contributions, and the BSIM4 model for MOS device. After a brief review of these models, as example of analog circuit, the proposed procedure is applied to study a basic current mirror and the simulation results allow to determine easily the different noise contribution of every single source. The software used is Advanced Design System (ADS) which is compatible with the Verilog-A programming language.

Keywords

Main Subjects

References

  1. Marani, R., Perri, G., “CNTFET Modelling for Electronic Circuit Design”, Electro Chemical Transactions, 23 (2009) 429 - 437.
  2. Gelao, G., Marani, R., Diana, R., Perri, G., “A Semi-Empirical SPICE Model for n-type Conventional CNTFETs”, IEEE Transactions on Nanotechnology, 10 (2011) 506-512.
  3. Marani, R., Perri, G., “A Compact, Semi-empirical Model of Carbon Nanotube Field Effect Transistors oriented to Simulation Software”, Current Nanoscience, 7 (2011) 245-253.
  4. Marani, R., Perri, G., “A DC Model of Carbon Nanotube Field Effect Transistor for CAD Applications”, International Journal of Electronics, 99 (2012) 427 - 444.
  5. Marani, R., Gelao, G., Perri, G., “Modelling of Carbon Nanotube Field Effect Transistors oriented to SPICE software for A/D circuit design”, Microelectronics Journal, 44 (2013) 33-39.
  6. Marani, R., Perri, G.,  “Modelling of CNTFETs for Computer Aided Design of A/D Electronic Circuits”, Current Nanoscience, 10 (2014) 326-333.
  7. Gelao, G., Marani, R., Pizzulli, L., Perri, G., “A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis”, Current Nanoscience, 11 (2015) 515-526.
  8. Gelao, G., Marani, R., Pizzulli, L., Perri, G., “A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part II: Dynamic Analysis”, Current Nanoscience, 11 (2015) 770-783.
  9. Marani, R., Perri, G.,  “Analysis of CNTFETs Operating in SubThreshold Region for Low Power Digital Applications”, ECS Journal of Solid State Science and Technology, 5(2) (2016) M1-M4.
  10. Marani, R., Perri, G.,  “A De-Embedding Procedure to Determine the Equivalent Circuit Parameters of RF CNTFETs”, ECS Journal of Solid State Science and Technology, 5(5) (2016) M31-M34.
  11. Marani, R., Perri, G., “A Simulation Study of Analogue and Logic Circuits with CNTFETs”, ECS Journal of Solid State Science and Technology, 5 (2016) M38-M43.
  12. Marani, R., Perri, G.,  “A Comparison of CNTFET Models through the Design of a SRAM Cell”, ECS Journal of Solid State Science and Technology, 5 (2016) M118-M126.
  13. Marani, R., Perri, G.,  “Design and Simulation Study of Full Adder Circuit Based on CNTFET and CMOS Technology by ADS”, ECS Journal of Solid State Science and Technology, 7 (2018) M108-M122.
  14. Marani, R., Perri, G., “Static Simulation of CNTFET-based Digital Circuits”, International Journal of Nanoscience and Nanotechnology, 14 (2018) 121-131.
  15. Marani, R., Perri, G., “Dynamic Simulation of CNTFET-based Digital Circuits”, International Journal of Nanoscience and Nanotechnology, 14 (2018) 277-288.
  16. Verilog-AMS language reference manual, Version 2.2, (2014).
  17. Marani, R., Perri, G., “Noise Effects in the Design of Analog Circuits Based on CNTFET”,  ECS Journal of Solid State Science and Technology, 11 (2022) 121010, doi: 10.1149/2162-8777/acad9f.
  18. http://bsim.berkeley.edu/models/bsim4/, BSIM Group, Berkeley, University of California, USA, (2020).
  19. Marani, R., Gelao, G., Perri, A. G., “A Compact Noise Model for C-CNTFETs”, ECS Journal of Solid State Science and Technology, 9 (2017) M118-126.
  20. Datta S., Cambridge Studies in Semiconductor Physics and Microelectronic Engineering 3. Electronic Transport in Mesoscopic Systems, New York: Cambridge University Press, Online ISBN: 978051180577, (1995).
  21. Van der Ziel A., Noise in Solid State Devices and Circuits, Wiley & Sons, New York, ISBN: 10:0471832340, (1986).
  22. Landauer G. M., Gonzalez J. L., “Carbon nanotube FET process variability and noise model for radiofrequency investigations”, Proceedings of 12th IEEE Int. Conference on Nanotechnology (IEEE-NANO), (2012), DOI:10.1109/nano.2012.6321963, Birmingham, UK.
  23. Landauer G. M., Gonzalez J. L., “A compact noise model for carbon nanotube FETs”, Proceedings of 2012 International Semiconductor Conference Dresden-Grenoble (ISCDG), (2012), DOI: 1109/ISCDG.2012.6360005.
  24. Hooge F. N., “1/f Noise sources”, IEEE Transactions on Electron Devices, 41 (1994), , 1926-1935, DOI: 10.1109/16.333808.
  25. http://ptm.asu.edu/.
  26. Marani, R., Perri, G., “Study of CNTFETs as Memory Devices”, ECS Journal of Solid State Science and Technology, 11 (2022),  031001, DOI:10.1149/2162-8777/ ac5846.
  27. Marani, R., Perri, G., “Review—Design of a Novel Full Adder Circuit based on CNTFET Technology”, ECS Journal of Solid State Science and Technology, 11 (2022), 051004, DOI:10.1149/2162-8777/ ac6d78.
  28. Gelao, G., Marani, R., Perri, G., “Study of Power Gain Capability of CNTFET Power Amplifier in THz Frequency Range”,  ECS Journal of Solid State Science and Technology, 11 (2022),  081005, DOI:10.1149/2162-8777/ ac84a7.
  29. Marani, R., Perri, G., “A Review on the Study of Temperature Effects in the Design of A/D Circuits based on CNTFET”, Current Nanoscience, 15 (2019), p. 471-480, DOI:10.2174/15734137 14666181009125058.
  30. Marani, R., Perri, G., “Temperature Dependence of I-V Characteristics in CNTFET Models: A Comparison”, International Journal of Nanoscience and Nanotechnology, 17(1), (2021), 33-39.
  31. Marani, R., Perri, G., “Review—Thermal Effects in the Design of CNTFET-Based Digital Circuits”, ECS Journal of Solid State Science and Technology, 11 (2022), 041006, DOI:10.1149/2162-8777/ ac63e6.
  32. Gelao, G., Marani, R., Perri, G.,  “A Formula to Determine Energy Band Gap in Semiconducting Carbon Nanotubes”, ECS Journal of Solid State Science and Technology, 8 (2019), p. M19-M21, DOI: 10.1149/2.0201902jss.
  33. Marani, R., Perri, G.,  “Comparative analysis of noise in current mirror circuits based on CNTFET and MOS Devices”, International Journal of Nanoscience and Nanotechnology, 17(2), (2021), 121-129.
  34. Marani, R., Perri, G., “Noise effects in the Design of Digital Circuits Based on CNTFET”, ECS Journal of Solid State Science and Technology, 11 (2022), 031006, DOI:10.1149/2162-8777/ ac5eb1.
  35. Marani, R., Perri, G., “Noise Effects in the Design of Analog Circuits Based on CNTFET”, ECS Journal of Solid State Science and Technology, 11 (2022),  121010, DOI:10.1149/2162-8777/ acad9f.
  36. Marani, R., Perri, G.,  “Editors’ Choice—Effects of Parasitic Elements of Interconnection Lines in CNT Embedded Integrated Circuits”, ECS Journal of Solid State Science and Technology, 9 (2020), 021004, DOI: 10.1149/2162-8777/ab69b2.
  37. Marani, R., Perri, G., “A Procedure to Analyze a CNTFET-based NOT gate with Parasitic Elements of Interconnection Lines”, International Journal of Nanoscience and Nanotechnology, 17(3), (2021), 161-171.
  38. Marani, R., Perri, G., “Impact of Technology on CNTFET-Based Circuits Performance”.  ECS Journal of Solid State Science and Technology, 9 (2020), 051001 DOI:10.1149/2162-8777/ ab9185.
  39. Gelao, G., Marani, R., Perri, G.,  “Analysis of Limits of CNTFET Devices through the Design of a Differential Amplifier”, ECS Journal of Solid State Science and Technology, 10 (2021), 061009, DOI:10.1149/2162-8777/ ac08df.
  40. Deng, J., Wong, H.-S. P., “A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region”, .IEEE Transactions on Electron Devices, 54 (2007) 3186-3194.
  41. Deng, J., Wong, H.-S. P., “A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking”, IEEE Transactions on Electron Devices, 54 (2007) 3195-3205.
  42. Lee, C-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S. P., “A Compact Virtual-Source Model for CarbonNanotube FETs in the Sub-10-nmRegime—Part I: Intrinsic Elements”, IEEE Transactions on Electron Devices, 62 (2015) 3061-3069.
  43. Lee, C-S., Pop, E., Franklin, A. D., Haensch, W., Wong, H.-S. P., “A Compact Virtual-Source Model for CarbonNanotube FETs in the Sub-10-nm Regime—Part II:Extrinsic Elements, Performance Assessment,and Design Optimization”, IEEE Transactions on Electron Devices, 62 (2015) 3070-3078.
International Journal of Nanoscience and Nanotechnology
Volume 19, Issue 1
March 2023
Pages 9-19

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