A Procedure to Analyze a CNTFET-Based ‎NOT Gate with Parasitic Elements of ‎Interconnection Lines

Document Type : Research Paper

Authors

1 ‎Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing ‎‎(STIIMA), National Research Council of Italy, 70125, Bari, Italy‎

2 ‎Electronic Devices Laboratory, Department of Electrical and Information Engineering, ‎Polytechnic University of Bari, 70126, Bari, Italy

Abstract

   In this paper we analyze an application of CNTFET in the design of NOT gate, in which parasitic elements of interconnection lines are considered. At first we study the time domain analysis of NOT gate without to consider the parasitic elements of interconnection lines, in order to compare the obtained results with those in which the parasitic elements are considered, showing how they limit the high-speed performances of CNTs.

Keywords

Main Subjects

References

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International Journal of Nanoscience and Nanotechnology
Volume 17, Issue 3
August 2021
Pages 161-171

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