Document Type : Research Paper
Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing (STIIMA), National Research Council of Italy, 70125, Bari, Italy
Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy
In this paper we analyze an application of CNTFET in the design of NOT gate, in which parasitic elements of interconnection lines are considered. At first we study the time domain analysis of NOT gate without to consider the parasitic elements of interconnection lines, in order to compare the obtained results with those in which the parasitic elements are considered, showing how they limit the high-speed performances of CNTs.