1
Consiglio Nazionale delle Ricerche, Istituto di Studi sui Sistemi Intelligenti per l'Automazione (ISSIA), Bari, Italy.
2
Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, Italy.
Abstract
In this paper we implement a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits. To verify the validity of the obtained results, they are compared with those of Wong model, resulting in good agreement, but obtaining a lighter ensuring compile and shorter execution time, which are the main characteristics to have an easy implementation in circuit simulators for CAD applications.
Marani,R. and Perri,A. G. (2018). Static Simulation of CNTFET-based Digital Circuits. International Journal of Nanoscience and Nanotechnology, 14(2), 121-131.
MLA
Marani,R. , and Perri,A. G. . "Static Simulation of CNTFET-based Digital Circuits", International Journal of Nanoscience and Nanotechnology, 14, 2, 2018, 121-131.
HARVARD
Marani R., Perri A. G. (2018). 'Static Simulation of CNTFET-based Digital Circuits', International Journal of Nanoscience and Nanotechnology, 14(2), pp. 121-131.
CHICAGO
R. Marani and A. G. Perri, "Static Simulation of CNTFET-based Digital Circuits," International Journal of Nanoscience and Nanotechnology, 14 2 (2018): 121-131,
VANCOUVER
Marani R., Perri A. G. Static Simulation of CNTFET-based Digital Circuits. International Journal of Nanoscience and Nanotechnology, 2018; 14(2): 121-131.
